This invention relates to electrically-erasable, electrically-programmable, read-only-memory arrays, and more particularly to a method for programming such arrays.
EPROMs, or electrically-programmable, read-only-memories, are field-effect devices having a floating-gate-type structure. An EPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing high current to flow through the source-drain path and charging the floating gate by hot electron injection. An EPROM device is erased by ultraviolet light, which requires a device package having a quartz window above the semiconductor chip. Packages of this type are expensive in comparison with the plastic packages ordinarily used for other integrated circuits. One such EPROM device is shown by U.S. Pat. No. 4,750,024, issued to John F. Schreck and assigned to Texas Instruments Incorporated.
EEPROMs, or electrically-erasable, electrically-programmable, read-only-memories, have been manufactured by various processes that usually require a much larger cell size than standard EPROMs and further require more complex manufacturing processes. EEPROMs can however be mounted in opaque plastic packages that reduce the packaging cost. Nevertheless, conventional EEPROMs have, on the whole, been more expensive on a per-bit basis.
More recently, a family of "flash" EEPROMs has been developed that allows an array of cells to be erased in bulk or in blocks instead of each cell being erased individually. Because these EEPROMs may be erased in bulk or in blocks, their cell size can be smaller.
To reduce cell size further and therefore the cost of manufacture, an EEPROM cell integrating a remotely located tunnelling area with a floating-gate transistor has recently been devised. The structural characteristics of the cell and its method of manufacture have been fully disclosed in parent application Ser. No. 07/494,042 and related applications. This application describes and claims a novel method for programming cells of the type disclosed as well as other types of non-volatile memory cells.
Prior-art programming procedures typically require that a preselected first programming voltage be placed on a selected one of a plurality of wordline rows that are spaced apart and formed over respective columns of memory cells. Each of the wordline conductors is insulated from and disposed adjacent to a floating gate conductor of each cell in the respective row. Also, as in prior-art procedures, a second preselected programming voltage that is substantially less positive than the first programming voltage is placed on a selected one of a plurality of elongate semiconductor bitlines formed in columns at an angle to the rows, with a column of memory cells being associated with each bitline. Where the selected wordline conductor intersects the selected bitline, electrons flow through a programming window insulator from the selected bitline to the floating gate conductor in the selected row to program the selected floating gate conductor. The drains of the cells are usually allowed to float.
During such programming, certain of the non-selected memory cells, particularly those in the same row, tend to become programmed. In prior-art memory arrays employing Fowler-Nordheim tunnelling, memory cells using two or three transistors have been used to avoid "write disturb" during programming.